From bad8be790fda049f2c9fb4bf72b36b3f8bcb62fa Mon Sep 17 00:00:00 2001
From: Martin Sekera <sekerama@gmail.com>
Date: Mon, 26 Apr 2021 21:25:14 +0200
Subject: [PATCH] sys-boot/u-boot: add patch for pinebook pro panel reset

---
 .../rk3399-pinebook-pro.edp-panel-reset.patch | 63 +++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 sys-boot/u-boot/files/rk3399-pinebook-pro.edp-panel-reset.patch

diff --git a/sys-boot/u-boot/files/rk3399-pinebook-pro.edp-panel-reset.patch b/sys-boot/u-boot/files/rk3399-pinebook-pro.edp-panel-reset.patch
new file mode 100644
index 0000000..6975996
--- /dev/null
+++ b/sys-boot/u-boot/files/rk3399-pinebook-pro.edp-panel-reset.patch
@@ -0,0 +1,63 @@
+From 352cb7b28bf4a16330f148043e8d10b0141bbfcb Mon Sep 17 00:00:00 2001
+From: Arnaud Patard <arnaud.patard@rtp-net.org>
+Date: Wed, 8 Jul 2020 21:43:36 -0400
+Subject: [PATCH 4/4] PBP: Fix panel reset
+
+On warm reset, the pinebook pro panel is not working correctly.
+The issue is not yet debugged so, for now, this hack seems to be
+enough. It toggles the GPIO1_C6 gpio [ LCDVCC_EN signal in the
+schematics ] used by the vcc3v3_panel regulator.
+
+There's no gpio_request, since the gpio is already in use at this
+stage, so it can only fail.
+
+Origin: http://people.hupstream.com/~rtp/pbp/20200706/patches/hack-reset.patch
+---
+ board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
+index 516292aaa59..ff9c916bcb7 100644
+--- a/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
++++ b/board/pine64/pinebook-pro-rk3399/pinebook-pro-rk3399.c
+@@ -7,13 +7,15 @@
+ #include <common.h>
+ #include <dm.h>
+ #include <syscon.h>
++#include <linux/delay.h>
++#include <asm/gpio.h>
+ #include <asm/io.h>
+ #include <asm/arch-rockchip/clock.h>
+ #include <asm/arch-rockchip/grf_rk3399.h>
++#include <asm/arch-rockchip/gpio.h>
+ #include <asm/arch-rockchip/hardware.h>
+ #include <asm/arch-rockchip/misc.h>
+ #include <power/regulator.h>
+-
+ #define GRF_IO_VSEL_BT565_SHIFT 0
+ #define PMUGRF_CON0_VSEL_SHIFT 8
+ 
+@@ -59,6 +61,7 @@ int misc_init_r(void)
+ 	const u32 cpuid_length = 0x10;
+ 	u8 cpuid[cpuid_length];
+ 	int ret;
++	unsigned int gpio;
+ 
+ 	setup_iodomain();
+ 
+@@ -70,6 +73,11 @@ int misc_init_r(void)
+ 	if (ret)
+ 		return ret;
+ 
++	gpio_lookup_name("B22", NULL, NULL, &gpio);
++	gpio_direction_output(gpio, 0);
++	udelay(500000);
++	gpio_direction_output(gpio, 1);
++
+ 	return ret;
+ }
+ #endif
+-- 
+2.25.4
+
+