rename sys-boot/u-boot -> sys-boot/u-boot-pbp, remove nanopi-m4v2 capability
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parent
559b1a65f8
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28256ec9db
5 changed files with 9 additions and 264 deletions
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@ -0,0 +1,50 @@
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From 08e8ace48b5c3a31b44661ef22a8b8a459906d7e Mon Sep 17 00:00:00 2001
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From: Nadia Holmquist Pedersen <nadia@nhp.sh>
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Date: Sat, 20 Jun 2020 01:49:49 +0200
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Subject: [PATCH 3/3] Enable the power LED during early startup
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---
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arch/arm/mach-rockchip/rk3399/rk3399.c | 12 +++++++++++-
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1 file changed, 11 insertions(+), 1 deletion(-)
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diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c
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index 4fda93b152..e24b39486d 100644
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--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
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+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
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@@ -19,6 +19,8 @@
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#include <asm/arch-rockchip/hardware.h>
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#include <linux/bitops.h>
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#include <power/regulator.h>
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/pinctrl/rockchip.h>
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DECLARE_GLOBAL_DATA_PTR;
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@@ -119,8 +121,8 @@ void board_debug_uart_init(void)
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struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
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#ifdef CONFIG_TARGET_CHROMEBOOK_BOB
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struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE;
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- struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
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#endif
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+ struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE;
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#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
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/* Enable early UART0 on the RK3399 */
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@@ -153,6 +155,14 @@ void board_debug_uart_init(void)
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spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL);
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#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */
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+ {
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+ // set GPIO0_A2/B3 to GPIO_ACTIVE_HIGH
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+ // set GPIO0_A2/B3 to OUTPUT
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+ int mask = (1UL << RK_PA2) | (1UL << RK_PB3);
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+ setbits_le32(&gpio->swport_dr, mask);
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+ setbits_le32(&gpio->swport_ddr, mask);
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+ }
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+
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/* Enable early UART2 channel C on the RK3399 */
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rk_clrsetreg(&grf->gpio4c_iomux,
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GRF_GPIO4C3_SEL_MASK,
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--
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2.27.0
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